How to improve the silicon nanocrystal memory cell performances for low power applications

V. Della Marca (1) , J. Amouroux (2) , G. Molas (3) , J. Postel-Pellerin (1) , F. Lalande (1) , P. Boivin (2) , E. Jalaguier (3) , B. de Salvo (3) , J.-L. Ogier (2)

1 IM2NP - Institut des Matériaux, de Microélectronique et des Nanosciences de Provence
2 ST-ROUSSET - STMicroelectronics [Rousset]
3 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information

In this paper we propose to optimize the 1T silicon nanocrystal (Si-nc) memory cell in order to reduce the energy consumption for low power applications. Optimized Channel Hot Electron Injection (a 4.5V programming window is reached consuming 1nJ) and Fowler-Nordheim programming are analyzed and compared. The tunnel oxide thickness, Si-ncs area coverage and SiN silicon nanocrystals capping layer are adjusted to optimize the data retention and endurance criteria. We present for the first time the endurance characteristics of a Si-nc cell up to 10 6 cycles with a final programming window of 4V.

Mots clés: Silicon nanocrystal memories; energy consumption; tunnel oxide thickness

Domaines: Micro et nanotechnologies/Microélectronique

V. Della Marca, J. Amouroux, G. Molas, J. Postel-Pellerin, F. Lalande, et al.. How to improve the silicon nanocrystal memory cell performances for low power applications. 2012 International Semiconductor Conference (CAS 2012), Oct 2012, Sinaia, Romania. ⟨10.1109/SMICND.2012.6400686⟩. ⟨hal-01760587⟩