Flash gate optimized process and integration for electrical performances requirement on advanced embedded memory

El Amine Agharben (1, 2, 3) , M. Bileci (1) , A. Roussy (4) , Marc Bocquet (2)

1 ST-ROUSSET - STMicroelectronics [Rousset]
2 IM2NP - Institut des Matériaux, de Microélectronique et des Nanosciences de Provence
3 Mines Saint-Étienne MSE - École des Mines de Saint-Étienne
4 EMSE-CMP - Ecole Nationale Supérieure des Mines de Saint-Etienne, Centre Microélectronique de Provenc

In this paper a correlation between specific inline and electrical parameters related to erase threshold voltage has been deeply investigated. This study shows the impact of the WL roughness on a NOR flash memory performances. A process recipe optimization and Run to Run feed-forward controller have been evaluated to keep the process in control.

Domaines: Micro et nanotechnologies/Microélectronique

El Amine Agharben, M. Bileci, A. Roussy, Marc Bocquet. Flash gate optimized process and integration for electrical performances requirement on advanced embedded memory. 2016 International Symposium on Semiconductor Manufacturing (ISSM), Dec 2016, Tokyo, Japan. ⟨10.1109/ISSM.2016.7934533⟩. ⟨hal-01737950⟩