Impact of the design layout on threshold voltage in SiGe channel UTBB-FDSOI pMOSFET

Rémy Berthelon (1) , F. Andrieu (2) , S. Ortolland (1) , R. Nicolas (1) , T. Poiroux (2) , E. Baylac (1) , D. Dutartre (1) , E. Josse (1) , Alain Claverie (3) , M. Haond (1)

1 ST-CROLLES - STMicroelectronics [Crolles]
2 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information
3 CEMES-MEM - Matériaux et dispositifs pour l'Electronique et le Magnétisme

The introduction of SiGe channel for pMOSFETs in FDSOI technology enables to achieve high performance. However, it has been demonstrated that such a global stressor induces layouts effects. In this paper, we present an exhaustive study of layout impact on threshold voltage. Especially, dissymmetric layouts, non-rectangular active areas and multifinger transistors are investigated. We propose an analytical model based on stress profile to reproduce the layout dependences. This model reproduces the experimental data with good accuracy, whatever the shape of the active area. © 2016 IEEE.

Mots clés: MOSFET devices; Silicon alloys; Stress analysis; Stresses; Design layout; FDSOI; Layout dependences; Layout effects; Multi-finger transistor; SiGe; SiGe channels; Stress profile; Threshold voltage

Domaines: Physique [physics]

Rémy Berthelon, F. Andrieu, S. Ortolland, R. Nicolas, T. Poiroux, et al.. Impact of the design layout on threshold voltage in SiGe channel UTBB-FDSOI pMOSFET. Ultimate Integration on Silicon (EUROSOI-ULIS), 2016 Joint International EUROSOI Workshop and International Conference on, 2016, Unknown, Unknown Region. pp.88-91, ⟨10.1109/ULIS.2016.7440059⟩. ⟨hal-01719488⟩