Hardware architecture for lowering the error floor of LTE turbo codes

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https://hal.archives-ouvertes.fr/hal-01702580
Contributor : Bertrand Le Gal <>
Submitted on : Tuesday, February 6, 2018 - 10:40:57 PM
Last modification on : Thursday, September 12, 2019 - 8:38:06 AM

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Thibaud Tonnellier, Camille Leroux, Bertrand Le Gal, Christophe Jego, Benjamin Gadat, et al.. Hardware architecture for lowering the error floor of LTE turbo codes. 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), Oct 2016, Rennes, France. ⟨10.1109/DASIP.2016.7853805⟩. ⟨hal-01702580⟩

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