Efficient Hardware Implementation of Probabilistic Gradient Descent Bit-Flipping

Khoa Le (1) , Fakhreddine Ghaffari (2) , David Declercq (1) , Bane Vasic (3)

1 ETIS - UMR 8051 - Equipes Traitement de l'Information et Systèmes
2 ASTRE [Cergy-Pontoise]
3 ECE - Department of Electrical and Computer Engineering [Tucson]

Domaines: Théorie de l'information et codage [math.IT]; Traitement du signal et de l'image [eess.SP]; Electronique

Khoa Le, Fakhreddine Ghaffari, David Declercq, Bane Vasic. Efficient Hardware Implementation of Probabilistic Gradient Descent Bit-Flipping. IEEE Transactions on Circuits and Systems I: Regular Papers, 2017, 64 (4), pp.906 - 917. ⟨10.1109/TCSI.2016.2633581⟩. ⟨hal-01700290⟩