A temperature-aware analysis of latched comparators for smart vehicle applications

Adriano V. Fonseca (1, 2) , Rachid El Khattabi (2) , William A Afshari (2) , Fernando a P Barúqui (1) , Carlos F T Soares (1) , Pietro M. Ferreira (2)

1 UFRJ - Universidade Federal do Rio de Janeiro [Brasil] = Federal University of Rio de Janeiro [Brazil] = Université fédérale de Rio de Janeiro [Brésil]
2 GeePs - Laboratoire Génie électrique et électronique de Paris

The challenges of the Internet of Things (IoT) in an urban environment are driven by smart vehicles which need to be able to efficiently sense and communicate with other nearby vehicles. System-on-chip (SoC) applications in the automotive market have strict circuit performances and reliability requirements for a temperature range of up to 175 °C. This work proposes an analysis of latched-comparators performance considering process variability and temperature variation. State-of-the-art StrongArm and Double-Tail comparators are designed using an XH018 technology. Post-layout simulation results are drawn in order to validate the proposed temperature-aware analysis. Besides the known advantages of the Double-Tail comparator, this work demonstrates that such a comparator has a serious drawback under harsh environments. At 175 °C, the Double-Tail presents a 3.1 ns worst case delay and 1.4 mV offset, while StrongArm shows 2.7 ns and 2.7 mV respectively. Moreover, the Double-Tail's input-referred noise achieves worst-case levels of 0.89 mV, the StrongArm's noise is below 0.4 mV. Therefore, the Double-Tail proved to be less reliable than the StrongArm and also foretells critical failure conditions in harsh environments.

Mots clés: temperature-aware; latched comparators; reliability; smart vehicle

Domaines: Micro et nanotechnologies/Microélectronique; Electronique

Adriano V. Fonseca, Rachid El Khattabi, William A Afshari, Fernando a P Barúqui, Carlos F T Soares, et al.. A temperature-aware analysis of latched comparators for smart vehicle applications. 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, Aug 2017, Fortaleza, Brazil. pp.1-6, ⟨10.1145/3109984.3109994⟩. ⟨hal-01656784⟩