Reduced Complexity FPGA Implementation for UF-OFDM Frequency Domain Transmitter

Saïd Medjkouh (1) , Jérémy Nadal (2, 1, 3) , Charbel Abdel Nour (2, 1, 3) , Amer Baghdadi (2, 1, 3)

1 IMT Atlantique - ELEC - Département Electronique
2 Lab-STICC_IMTA_CACS_IAS
3 Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance

Universal Filtered Orthogonal Frequency Division Multiplexing (UF-OFDM) is considered one of the main waveform candidates to overcome the challenges facing the next generation of mobile communication systems. Due to its spectral properties it can support relaxed synchronization, low-latency communications and flexible time transmission interval. Nevertheless, the available recent literature addresses the potential of this waveform mainly from communication performance perspective, and sometimes presents a rough estimation of the complexity. Therefore, it becomes high of interest to seek efficient hardware implementations. In this paper, a reduced complexity pipelined architecture is proposed for UF-OFDM frequency domain transmitter. Using LTE parameters, the proposed UFOFDM FDA architecture uses around 3.6 times less hardware ressources than the straightforward implementation.

Mots clés: UF-OFDM; OFDM; 5G; FPGA

Domaines: Théorie de l'information [cs.IT]; Electronique; Traitement du signal et de l'image [eess.SP]

Saïd Medjkouh, Jérémy Nadal, Charbel Abdel Nour, Amer Baghdadi. Reduced Complexity FPGA Implementation for UF-OFDM Frequency Domain Transmitter. SIPS 2017: IEEE Workshop on Signal Processing Systems, Oct 2017, Lorient, France. pp.1 - 6, ⟨10.1109/SiPS.2017.8110013⟩. ⟨hal-01656134⟩