Metastability Tolerant Computing

Ghaith Tarawneh 1 Matthias Függer 2, 3, 4 Christoph Lenzen 5
4 MEXICO - Modeling and Exploitation of Interaction and Concurrency
LSV - Laboratoire Spécification et Vérification [Cachan], ENS Cachan - École normale supérieure - Cachan, Inria Saclay - Ile de France, CNRS - Centre National de la Recherche Scientifique : UMR8643
Abstract : Synchronization using flip-flop chains imposes a latency of a few clock cycles when transferring data and control signals between clock domains. We propose a design scheme that avoids this latency by performing synchronization as part of state/data computations while guaranteeing that metastability is contained and its effects tolerated (with an acceptable failure probability). We present a theoretical framework for modeling synchronous state machines in the presence of metastability and use it to prove properties that guarantee some form of reliability. Specifically, we show that the inevitable state/data corruption resulting from propagating metastable states can be confined to a subset of computations. Applications that can tolerate certain failures can exploit this property to leverage low-latency and quasi-reliable operation simultaneously. We demonstrate the approach by designing a Network-on-Chip router with zero-latency asynchronous ports and show via simulation that it outperforms a variant with two flip-flop synchronizers at a negligible cost in packet transfer reliability.
Type de document :
Communication dans un congrès
ASYNC17 - 23rd IEEE International Symposium on Asynchronous Circuits and Systems, May 2017, San Diego, United States
Liste complète des métadonnées

Littérature citée [24 références]  Voir  Masquer  Télécharger
Contributeur : Matthias Függer <>
Soumis le : jeudi 30 novembre 2017 - 16:31:25
Dernière modification le : jeudi 11 janvier 2018 - 06:27:34


Fichiers produits par l'(les) auteur(s)


  • HAL Id : hal-01652772, version 1


Ghaith Tarawneh, Matthias Függer, Christoph Lenzen. Metastability Tolerant Computing. ASYNC17 - 23rd IEEE International Symposium on Asynchronous Circuits and Systems, May 2017, San Diego, United States. 〈hal-01652772〉



Consultations de la notice


Téléchargements de fichiers