Extended-Forward Architecture for Simplified Check Node Processing in NB-LDPC Decoders

Cédric Marchand (1) , Emmanuel Boutillon (2) , Hassan Harb (1) , Laura Conde-Canencia (3) , Ali Al Ghouwayel (4)

1 Lab-STICC_UBS_CACS_IAS
2 Lab-STICC_UBS_CACS_IAS
3 Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (UMR 3192)
4 LIU - Lebanese International University

This paper focuses on low complexity architectures for check node processing in Non-Binary LDPC decoders. To be specific, we focus on Extended Min-Sum decoders and consider the state-of-the-art Forward-Backward and Syndrome-Based approaches. We recall the presorting technique that allows for significant complexity reduction at the Elementary Check Node level. The Extended-Forward architecture is then presented as an original new architecture for efficient syndrome calculation. These advances lead to a new architecture for check node processing with reduced area. As an example, we provide implementation results over GF(64) and code rate 5/6 showing complexity reduction by a factor of up to 2.6.

Mots clés: NB-LDPC; Check Node; Syndrome-Based; Foward-Backward; VLSI

Domaines: Electronique

Cédric Marchand, Emmanuel Boutillon, Hassan Harb, Laura Conde-Canencia, Ali Al Ghouwayel. Extended-Forward Architecture for Simplified Check Node Processing in NB-LDPC Decoders. SIPS'2017, Oct 2017, Lorient, France. ⟨hal-01613799⟩