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Hierarchical Static Timing Analysis at Bull with HiTas

Abstract : This paper describes the method used in the design of a 26 million transistors chip at BULL to verify the timing performance using the hierarchical timing analysis tool HiTas as well as the interactive path browser Xtas. Those tools have been designed at UPMC and are now commercialized by AVERTEC. The complexity is handled by partitioning the analysis according to the hierarchical partitioning of the design phase. The propagation times within a circuit are represented using a multi-level hierarchical timing view.
Document type :
Conference papers
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https://hal.archives-ouvertes.fr/hal-01573604
Contributor : Lip6 Publications <>
Submitted on : Thursday, August 10, 2017 - 10:08:19 AM
Last modification on : Thursday, March 21, 2019 - 12:59:57 PM

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  • HAL Id : hal-01573604, version 1

Citation

Karim Dioury, Anthony Lester, Alain Debreil, Grégoire Avot, Alain Greiner, et al.. Hierarchical Static Timing Analysis at Bull with HiTas. Design Automation and Test in Europe Conference User Forum (DATE'2000), Mar 2000, Paris, France. pp.55-60. ⟨hal-01573604⟩

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