Testing TAPed Cores and Wrapped Cores With The Same Test Access Mechanism

Mounir Benabdenbi (1) , Walid Maroufi (1) , Meryem Marzouki (1)

1 ASIM - Architecture des Systèmes intégrés et Micro électronique

This paper describes a way of testing both wrapped cores and TAPed cores within a System On a Chip (SoC) with the same Test Access Mechanism (TAM). The TAM's architecture, which is dynamically reconfigurable, scalable and flexible, is named CAS-BUS and have a central controller. All the cores can be tested this way in the same session through a modified Boundary Scan Test Access Port.

Domaines: Informatique [cs]

Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki. Testing TAPed Cores and Wrapped Cores With The Same Test Access Mechanism. DATE 2001 - IEEE Design Automation and Test in Europe, Mar 2001, Munich, Germany. pp.150-155, ⟨10.1109/DATE.2001.915016⟩. ⟨hal-01571032⟩