Testing TAPed Cores and Wrapped Cores With The Same Test Access Mechanism

Abstract : This paper describes a way of testing both wrapped cores and TAPed cores within a System On a Chip (SoC) with the same Test Access Mechanism (TAM). The TAM's architecture, which is dynamically reconfigurable, scalable and flexible, is named CAS-BUS and have a central controller. All the cores can be tested this way in the same session through a modified Boundary Scan Test Access Port.
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Conference papers
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https://hal.archives-ouvertes.fr/hal-01571032
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Submitted on : Tuesday, August 1, 2017 - 2:31:53 PM
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  • HAL Id : hal-01571032, version 1

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Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki. Testing TAPed Cores and Wrapped Cores With The Same Test Access Mechanism. DATE 2001 - IEEE Design Automation and Test in Europe, Mar 2001, Munich, Germany. pp.150-155. ⟨hal-01571032⟩

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