Protocol and Performance Analysis of the MPC Parallel Computer

Olivier Glück 1 Amal Zerrouki Jean-Lou Desbarbieux Alexandre Fenyö 1 Alain Greiner 1 Franck Wajsbürt 1 Cyril Spasevski 1 Fabricio Silva Emmanuel Dreyfus
1 ASIM - Architecture des Systèmes intégrés et Micro électronique
LIP6 - Laboratoire d'Informatique de Paris 6
Abstract : This paper presents the MPC parallel computer and its MPI implementation performed at the Laboratoire LIP6 of Univ. Pierre and Marie Curie, Paris. MPC is a low cost and high performance parallel computer using standard PC main-boards as processing nodes connected through the specific FastHSL board to a high speed communication network using HSL 1 Gbits/s serial links, IEEE 1355 compliant. Two Asics are presented: RCUBE which is the HSL network router and PCI-DDC the network controller implementing the Direct Deposit State Less receiver protocol. The software part of the MPC parallel computer consists of 2 zero-copy layers leading to a latency of 5 to 40 /spl mu/s and a throughput of 490 Mbits/s. An efficient MPI implementation based on MPICH is presented and evaluated on an MPC parallel computer. Measures show a latency of 26 /spl mu/s and an useful throughput of 450 Mbits/s This paper presents also a performances study of the MPI implementation on the MPC computer. This reveals Several possible optimizations to reduce the overall MPI transfer latency on the MPC Computer.
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Conference papers
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https://hal.archives-ouvertes.fr/hal-01571021
Contributor : Lip6 Publications <>
Submitted on : Tuesday, August 1, 2017 - 2:24:00 PM
Last modification on : Thursday, March 21, 2019 - 1:13:31 PM

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LIP6 | UPMC | SORBONNE-UNIVERSITE | SU-SCIENCES

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Olivier Glück, Amal Zerrouki, Jean-Lou Desbarbieux, Alexandre Fenyö, Alain Greiner, et al.. Protocol and Performance Analysis of the MPC Parallel Computer. 15th International Parallel and Distributed Processing Symposium (IPDPS 2001), Apr 2001, San Francisco, CA, United States. ⟨10.1109/IPDPS.2001.924994⟩. ⟨hal-01571021⟩

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