A Complete Automatic Test Set Generator for Embedded Reactive Systems: From AUTSEG V1 to AUTSEG V2

Mariem Abdelmoula (1) , Daniel Gaffé (1) , Michel Auguin (1)

1 LEAT - Laboratoire d'Electronique, Antennes et Télécommunications

One of the biggest challenges in hardware and software design is to ensure that a system is error-free. Small defects in reactive embedded systems can have disastrous and costly consequences for a project. Preventing such errors by identifying the most probable cases of erratic system behavior is quite challenging. Indeed, tests performed in industry are non-exhaustive, while state space analysis using formal verification in scientific research is inappropriate for large complex systems. We present in this context a new approach for generating exhaustive test sets that combines the underlying principles of the industrial testing technique with the academic-based formal verification. Our method consists in building a generic model of the system under test according to the synchronous approach. The goal is to identify the optimal preconditions for restricting the state space of the model such that test generation can take place on significant subspaces only. So, all the possible test sets are generated from the extracted subspace preconditions. Our approach exhibits a simpler and efficient quasi-flattening algorithm compared with existing techniques, and a useful compiled internal description to check security properties while minimizing the state space combinatorial explosion problem. It also provides a symbolic processing technique for numeric data that provides an expressive and concrete test of the system, while improving system verification (Determinism, Death sequences) and identifying all possible test cases. We have implemented our approach on a tool called AUTSEG V2. This testing tool is an extension of the first version AUTSEG V1 to integrate data manipulations. We present in this paper a complete description of our automatic testing approach including all features presented in AUTSEG V1 and AUTSEG V2.

Mots clés: Quasi-flattening; SupLDD; AUTSEG; Test Sets Generation; Backtrack

Domaines: Systèmes embarqués

Mariem Abdelmoula, Daniel Gaffé, Michel Auguin. A Complete Automatic Test Set Generator for Embedded Reactive Systems: From AUTSEG V1 to AUTSEG V2. International Journal On Advances in Systems and Measurements, 2016, 9 (3-4), pp.154-166. ⟨hal-01564594⟩