A distributed synchronization of all-digital PLLs network for clock generation in synchronous SOCs

Abstract : This paper presents a Cartesian network of CMOS oscillators distributed on a chip and synchronized by a network of all-digital PLLs in phase and in frequency. Such a network may be used for generation of a global clock in large digital systems on chip. The originality of the work is in the use of a solution essentially based on digital circuits. This offers many opportunities for implementation of different algorithms of synchronization, depending on the application context and operational conditions. The synchronization algorithm is based on a PI control applied to the phase error measured between neighbors. In this way, the global synchronization is achieved through a local control: such an architecture is compatible with the concept of networks on chip, a largely spread concept in the worlds of VLSI circuits. The paper presents two prototypes demonstrating the feasibility and reliability of the proposed solution for synchronization.
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Communication dans un congrès
New Circuits and Systems Conference (NEWCAS), 2015 IEEE 13th International, Jun 2015, Grenoble, France. 〈http://ieeexplore.ieee.org/document/7182059/〉. 〈10.1109/NEWCAS.2015.7182059〉
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https://hal.archives-ouvertes.fr/hal-01521883
Contributeur : Dimitri Galayko <>
Soumis le : vendredi 12 mai 2017 - 14:35:25
Dernière modification le : lundi 24 septembre 2018 - 10:56:04

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Chuan Shan, Eldar Zianbetov, François Anceau, Olivier Billoint, Dimitri Galayko. A distributed synchronization of all-digital PLLs network for clock generation in synchronous SOCs. New Circuits and Systems Conference (NEWCAS), 2015 IEEE 13th International, Jun 2015, Grenoble, France. 〈http://ieeexplore.ieee.org/document/7182059/〉. 〈10.1109/NEWCAS.2015.7182059〉. 〈hal-01521883〉

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