Discrete-time modelling and experimental validation of an All-Digital PLL for clock-generating networks

Abstract : In this paper, we derive a mathematical model of an All-Digital Phase-Locked Loop (ADPLL) employing a time-to-digital phase detector. The model we suggest represents a nonlinear discrete-time map and provides significant benefits for the simulation of a single PLL, a network of PLLs or their design. In particular, the model allows us to take into account the jitter of the reference and local clocks and other noises. The mathematical model (the map) is then compared with a behavioural model implemented in MATLAB Simulink and displays identical results. The simulation of the mathematical and behavioural models are further compared with experimental measurements of a 65nm CMOS ADPLL and show a good agreement.
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Submitted on : Friday, May 12, 2017 - 11:30:19 AM
Last modification on : Thursday, March 21, 2019 - 2:33:46 PM

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Koskin Eugene, Elena Blokhina, Chuan Shan, Eldar Zianbetov, Orla Feely, et al.. Discrete-time modelling and experimental validation of an All-Digital PLL for clock-generating networks. New Circuits and Systems Conference (NEWCAS), 2016 14th IEEE International, IEEE-CASS, Jun 2016, Vancouver, BC, Canada. ⟨10.1109/NEWCAS.2016.7604784⟩. ⟨hal-01521744⟩

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