A survey of NoC evaluation platforms on FPGAs
Résumé
Networks-on-chip (NoCs) have become a de facto
communication standard for many core systems-on-chip (SoCs).
A NoC has large design space composed of several parameters
such as routing algorithm, task mapping, flow control method,
among others. SoC designers deeply rely on automatic evaluation
tools in order to deal with the complexity of NoC design. An
important class of NoCs evaluation tools are the platforms based
on FPGAs, which improve the evaluation time and precision
when compared to other solutions like software simulators and
analytical models. In this paper, we survey propositions of
FPGA tools for NoC evaluation by using a layered model, which
covers aspects like network architecture, traffic generation and
interface to the host PC