Soft timing closure for soft programmable logic cores: The ARGen approach

Théotime Bollengier 1 Loïc Lagadec 2, 3 Mohamad Najem 2, 3 Jean-Christophe Le Lann 2, 3 Pierre Guilloux 4
2 Lab-STICC_ENSTAB_ CACS_MOCS
Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance
3 Pôle STIC_IDM
ENSTA Bretagne - École Nationale Supérieure de Techniques Avancées Bretagne
4 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources
Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE
Abstract : Reconfigurable cores support post-release updates which shortens time-to-market while extending circuits’ lifespan. Reconfigurable cores can be provided as hard cores (ASIC) or soft cores (RTL). Soft reconfigurable cores outperform hard reconfigurable cores by preserving the ASIC synthesis flow, at the cost of lowering scalability but also exacerbating timing closure issues. This article tackles these two issues and introduces the ARGen generator that produces scalable soft reconfigurable cores. The architectural template relies on injecting flip-flops into the interconnect, to favor easy and accurate timing estimation. The cores are compliant with the academic standard for place and route environment, making ARGen a one stop shopping point for whoever needs exploitable soft reconfigurable cores.
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https://hal.archives-ouvertes.fr/hal-01475251
Contributor : Loic Lagadec <>
Submitted on : Thursday, February 23, 2017 - 3:25:41 PM
Last modification on : Tuesday, February 4, 2020 - 2:00:09 PM
Long-term archiving on: Wednesday, May 24, 2017 - 2:04:00 PM

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Théotime Bollengier, Loïc Lagadec, Mohamad Najem, Jean-Christophe Le Lann, Pierre Guilloux. Soft timing closure for soft programmable logic cores: The ARGen approach . ARC 2017 - 13th International Symposium on Applied Reconfigurable Computing, Delft University of Technology Apr 2017, Delft, Netherlands. ⟨hal-01475251⟩

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