Minimizing test frequencies for linear analog circuits: new models and efficient solution methods

M. Bentobache (1) , Ahcène Bounceur (1) , R. Euler (1) , Salvador Mir (2) , Y. Kieffer (1)

1 UBO - Université de Brest
2 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés

This work presents new approaches to minimize the number of test frequencies for linear analog circuits. The cases of single and multiple fault detection regions for multiple test measures are considered. We first address the case when the injected faults have a single detection region in the frequency band. We show that the problem can be formulated as a set covering problem with a matrix having the consecutive-ones property for which the network simplex algorithm turns out to be very efficient. A second approach consists in modeling the problem by means of an interval graph, leading to its solution with a specific polynomialtime algorithm. A case-study of a biquadratic filter is presented for illustration purposes. Numerical simulations demonstrate that the two different approaches solve the optimization problem very fast. Finally, the optimization problems arising from multiple detection regions are modeled and solution approaches are discussed.

Domaines: Micro et nanotechnologies/Microélectronique

M. Bentobache, Ahcène Bounceur, R. Euler, Salvador Mir, Y. Kieffer. Minimizing test frequencies for linear analog circuits: new models and efficient solution methods. in VLSI-SoC: At the Crossroads of Emerging Trends, springer pp.188-207, 2015, 978-3-319-23799-2. ⟨10.1007/978-3-319-23799-29⟩. ⟨hal-01469204⟩