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CMOS differential neural amplifier with high input impedance

Abstract : We present a CMOS differential neural amplifier with high input impedance, which topology is inspired by the instrumentation amplifier. The miniaturization of the MEAs goes with an increase of the electrodes impedance and necessitates high input impedance neural amplifiers; otherwise it results in a significant loss of signal and low SNR. The circuit presented here is designed on a 0.35 μm CMOS technology. Two versions are described which capacitive input impedance is 1 pF. One is robust to high input offset and consumes 13.5 μA; the other one is more sensitive to offset but consumes only 3.7 μA. Both generate less than 7 μVRMS input-referred noise and their NEF figures are respectively 8.4 and 3.66. These features are competitive in view of the literature on neural amplifiers, while the circuit was specifically designed to present a high input impedance.
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Contributor : Noëlle Lewis <>
Submitted on : Tuesday, February 14, 2017 - 12:29:12 PM
Last modification on : Monday, March 30, 2020 - 2:20:07 PM



Francois Rummens, Sylvie Renaud, Noelle Lewis. CMOS differential neural amplifier with high input impedance. 2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS), 2015, Grenoble, France. ⟨10.1109/NEWCAS.2015.7182037⟩. ⟨hal-01467331⟩



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