High-Density 3-D Capacitors for Power Systems On-Chip: Evaluation of a Technology Based on Silicon Submicrometer Pore Arrays Formed by Electrochemical Etching

Magali Brunet (1) , Pascal Kleimann (2)

1 LAAS-ISGE - Équipe Intégration de Systèmes de Gestion de l'Énergie
2 INL - LOCI - INL - Lab-On-Chip et Instrumentation

This paper presents the state of the art technologies currently used to produce high density integrated capacitors for power systems on-chip applications. The use of high-k dielectrics and 3D patterning of silicon for reaching high specific capacitance is reviewed. Integrating capacitors monolithically on the active chip or in package of power systems is discussed and solutions are proposed for minimising series resistance and achieving a high level of integration. A technology based on nanolithography and silicon electrochemical etching is then detailed. It is shown that capacitance densities of up to 700 nF/mm² can be obtained with a submicrometer pores array in a relatively limited thickness. The advantages and disadvantages of further decreasing the pore size to nanosize pores (below 100 nm) are discussed.

Mots clés: wafer-level encapsulation; Electrochemical Double Layer Capacitor; Microsystem; high energy

Domaines: Micro et nanotechnologies/Microélectronique

Magali Brunet, Pascal Kleimann. High-Density 3-D Capacitors for Power Systems On-Chip: Evaluation of a Technology Based on Silicon Submicrometer Pore Arrays Formed by Electrochemical Etching. IEEE Transactions on Power Electronics, 2013, 28 (9), pp. 4440-4448. ⟨10.1109/TPEL.2012.2233219⟩. ⟨hal-01443216⟩