Real-Time Soft-Error Testing of 40nm SRAMs

Jean-Luc Autran (1) , S. Serre , Daniela Munteanu (1) , S. Martinie (1) , S. Semikh , S. Sauze (1) , S. Uznanski , G. Gasiot (2) , P. Roche (2)

1 IM2NP - Institut des Matériaux, de Microélectronique et des Nanosciences de Provence
2 ST-CROLLES - STMicroelectronics [Crolles]

This work reports the real-time Soft-Error Rate (SER) characterization of more than 7 Gbit of SRAM circuits manufactured in 40 nm CMOS technology and subjected to natural radiation (atmospheric neutrons). This experiment has been conducted since March 2011 at mountain altitude (2552 m of elevation) on the ASTEP Platform. The first experimental results, cumulated over more than 7,500 h of operation, are analyzed in terms of single bit upset, multiple cell upsets, physical bitmap and convergence of the SER. The comparison of the experimental data with Monte Carlo simulations and accelerated tests is finally reported and discussed.

Domaines: Micro et nanotechnologies/Microélectronique

Jean-Luc Autran, S. Serre, Daniela Munteanu, S. Martinie, S. Semikh, et al.. Real-Time Soft-Error Testing of 40nm SRAMs. 2012 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2012, Anaheim, CA, United States. ⟨10.1109/IRPS.2012.6241814⟩. ⟨hal-01430086⟩