STESI: Testing wrapped IP cores using a dedicated Test Processor

Matthieu Tuna (1) , Mounir Benabdenbi (1) , Alain Greiner (1)

1 ALSOC - Architecture et Logiciels pour Systèmes Embarqués sur Puce

This paper presents STESI, a software-based approach for testing SoCs containing wrapped IP cores. In the proposed approach, the test program is no more executed by the traditional ATE but by the SoC itself. The novel feature of the STESI approach is the use of a dedicated test coprocessor embedded on the SoC to test the remaining components. Using the ITC02 SoC benchmarks a comparison is done between the STESI architecture and a classical bus-based strategy.

Domaines: Informatique [cs]

Matthieu Tuna, Mounir Benabdenbi, Alain Greiner. STESI: Testing wrapped IP cores using a dedicated Test Processor. I-IP IEEE International Workshop on Infrastructure IP, May 2005, Palm Springs, California, United States. pp.60-66. ⟨hal-01418361⟩