Vector decision diagrams for simulation of digital systems
Résumé
Decision diagrams (DD) present a suitable way for the digital system representation efficiently used in several steps of the entire design cycle : for design verification, test generation and fault simulation. They offer a competitive simulation performance in comparison to the event-driven HDL-based simulation ; however, their initial complexity does not allow to favorably compare their performance with the algorithmic functional description of the circuit's behavior. This article presents the optimization of the DD representation aimed at improving their simulation efficiency. Two types of DDs are introduced : vector decision diagrams (VDDs) and compressed VDDs as an efficient and concise model of system behavior, which preserves all the advantages of the decision diagrams. Their computational complexity is similar to the algorithmic description. The results of the comparisons between the different types of DDs and the algorithmic representation are included. This comparison is based on the symbolic complexity measure, defined for that purpose.
