Techniques for improving the HDL simulation performance
Résumé
A growing complexity of the electronic systems stimulated by the progress in the fabrication technology of integrated circuits requires a corresponding growth of the productivity of the design and verification methods. The low simulation performance is one of the obstacles preventing a delivery of high quality of products in a short time and at a low cost. This article presents four methods developed for improving the simulation performance of VHDL models: the model optimisation, the model transformation, the model reduction and the model abstraction. These methods convert an initial VHDL model into another VHDL model, functionally equivalent, which renders a better simulation performance. The results of simulation time improvement of each method are presented.
