Design of an on-chip stepwise ramp generator for ADC static BIST applications

G. Renaud (1) , Manuel J. Barragan (1) , Salvador Mir (1)

1 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés

This work presents guidelines for the design of an on-chip ramp signal generator for static Built-In Self-Test (BIST) of ADCs. The proposed ramp generator is based on a fully-differential switched-capacitor (SC) integrator conveniently modified to produce a very small integration gain. The main non-idealities affecting the linearity of the generator are discussed on a practical implementation in a 65nm CMOS technology. Electrical simulation results at transistor level are provided to verify the feasibility and performance of the proposed approach.

Mots clés: built-in self test; CMOS-integrated-circuits

Domaines: Micro et nanotechnologies/Microélectronique

G. Renaud, Manuel J. Barragan, Salvador Mir. Design of an on-chip stepwise ramp generator for ADC static BIST applications. IEEE International Mixed-Signal Testing Workshop (IMS3TW'15), Jun 2015, Paris, France. pp.1-6. ⟨hal-01393841⟩