Synthesis of QDI asynchronous circuits from DTL-style petri-net

Laurent Fesquet (1) , Anh Vu Dinh Duc (1) , M. Renaudin (1)

1 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés

In this paper, a general methodology for synthesizing Quasi-Delay Insensitive (QDI) asynchronous circuits is presented. It starts from a Peri Net model reinforced by the DataTransfer Level (DTL) specification. Even though QDI circuit is the main focus of the paper, DTL-based synthesis can apply to any style of asynchronous circuits. The main steps of the compilation process are described. As an illustration, an example is studied and processed in details.

Mots clés: asynchronous circuits and systems

Domaines: Micro et nanotechnologies/Microélectronique

Laurent Fesquet, Anh Vu Dinh Duc, M. Renaudin. Synthesis of QDI asynchronous circuits from DTL-style petri-net. 11th IEEE/ACM International Workshop on Logic & Synthesis (IWLS'02), Jun 2002, New Orleans, Louisiana, États-Unis. ⟨hal-01391638⟩