Power consumption analysis for mesh based FPGA

Sonda Chtourou 1 Mohamed Abid 2 Zied Marrakchi 3 Habib Mehrez 3
2 CES
CES Lab - Computer & Embedded Systems
3 CIAN - Circuits Intégrés Numériques et Analogiques
LIP6 - Laboratoire d'Informatique de Paris 6
Abstract : This paper presents the power consumption analysis of two different routing architectures for mesh based FPGAs. The first architecture uses bidirectional Switch Box (SB) implemented using back-to-back tri-state drivers. The second one uses bidirectional SB implemented using tri-states and multiplexers. This paper highlights and experimentally demonstrates the benefit that can be reached by using multiplexers instead of back-to-back tri-state. In fact, total power consumption is reduced by around 23.5% with 0,13 μm technology which provides transistor with low leakage power and realizes 47% power savings with 0,18 μm technology. This benefit is due to a reduction in term of leakage power consumed by routing resource.
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Conference papers
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https://hal.archives-ouvertes.fr/hal-01372620
Contributor : Habib Mehrez <>
Submitted on : Tuesday, September 27, 2016 - 2:37:31 PM
Last modification on : Thursday, March 21, 2019 - 2:32:44 PM

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Sonda Chtourou, Mohamed Abid, Zied Marrakchi, Habib Mehrez. Power consumption analysis for mesh based FPGA. DTIS 2014 - 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, May 2014, Santorini, Greece. pp.1--5, ⟨10.1109/DTIS.2014.6850671⟩. ⟨hal-01372620⟩

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