The effect of interconnect depopulation on FPGA performances in terms of power, area and delay

Sonda Chtourou (1) , Mohamed Abid (2) , Zied Marrakchi (3) , Emna Amouri (4) , Habib Mehrez (4)

1 FSEG
2 CES Lab - Computer & Embedded Systems
3 Flexras Technologies
4 CIAN - Circuits Intégrés Numériques et Analogiques

The interconnect structure in common FPGA architectures is generally designed to maximize logic utilization. A fully populated routing interconnect is simple and provides high flexibility at the cost of power and area overhead. Moreover, the utilization rate of interconnect switches is extremely low. In this paper, we aim to explore new cluster-based mesh FPGA architectures with depopulated routing network. First, we propose a Depopulated FPGA (DFPGA) architecture with depopulated intra-cluster and inter-cluster interconnects. Based on a comparison with a common Mesh architecture, we note that power and area are improved respectively by an average of 23% and 30%. However, these improvements are obtained at the cost of wiring complexity, congestion and low flexibility to route complex circuits. To alleviate those weaknesses, we propose to populate inter-cluster interconnect by using hierarchy. We show experimentally that the second proposed FPGA architecture with Multilevel Switch blocks (MS-FPGA) has a good routability and interesting power consumption and area density compared to the common cluster-based mesh FPGA. Moreover, additional switches used in the hierarchical inter-cluster interconnect of the MSFPGA are compensated with a better flexibility. Unlike DFPGA, MS-FPGA can deal with complex circuits.

Domaines: Architectures Matérielles [cs.AR]

Sonda Chtourou, Mohamed Abid, Zied Marrakchi, Emna Amouri, Habib Mehrez. The effect of interconnect depopulation on FPGA performances in terms of power, area and delay. HPCS 2016 - International Conference on High Performance Computing & Simulation, Jul 2016, Innsbruck, Austria. pp.104--111, ⟨10.1109/HPCSim.2016.7568322⟩. ⟨hal-01372560⟩