Mesh of Clusters FPGA Architectures: Exploration Methodology and Interconnect Optimization

Sonda Chtourou (1) , Zied Marrakchi (2, 3) , Vinod Pangracious (3) , Emna Amouri (4) , Habib Mehrez (3) , Mohamed Abid (5)

1 FSEG
2 Flexras Technologies
3 CIAN - Circuits Intégrés Numériques et Analogiques
4 Télécom ParisTech
5 CES Lab - Computer & Embedded Systems

In this paper, we present an improved Mesh of Clusters (MoC) architecture with new hierarchical Switch Box (SB) topology and depopulated intra-cluster interconnect with flexible Rent’s parameter. The aim of this paper is to explore the effect of different architecture parameters like architecture Rent’s, design Rent’s and channel width. Then, we analyze how these factors interact and the way to tune them to satisfy various specific application constraints and quality metrics like power consumption and area. The proposed exploration methodology unifies two procedures which are analytical method based on Rent’s rule modeling and experimental method based on benchmarks circuits implementation. A comparison with VPR mesh architecture shows gains in terms power and area equal respectively to 30% and 32%.

Domaines: Architectures Matérielles [cs.AR]

Sonda Chtourou, Zied Marrakchi, Vinod Pangracious, Emna Amouri, Habib Mehrez, et al.. Mesh of Clusters FPGA Architectures: Exploration Methodology and Interconnect Optimization. ARC 2015 - 11th International Symposium on Applied Reconfigurable Computing, Apr 2015, Bochum, Germany. pp.411-418, ⟨10.1007/978-3-319-16214-0_37⟩. ⟨hal-01369176⟩