Design and Optimization of a Horizontally Partitioned, High-Speed, 3D Tree-Based FPGA

Abstract : The authors explore and design the traditional field-programmable gate array (FPGA) interconnect topologies and architectures that can play an important role in improving performance and density. The main architectures under exploration are tree-based and island-style Manhattan Mesh. Mesh-based design is the most common industrial and academic architecture. Numerous research and industrial designs have been developed to improve mesh-based FPGAs' performance, area, and power consumption. Nonetheless, when looking at performance metrics such as speed, area, and power, the gap is generally very wide for FPGAs compared to application-specific integrated circuits (ASICs). Despite their good properties, such as high logic density and area advantage, tree-based architectures have been overlooked up to now. This article addresses long wire length issues associated with tree-based programmable interconnects using 3D design and manufacturing technologies. Using their dedicated 3D design and optimization methodology, the authors show that 3D tree-based architecture is 1.5 times faster than the mesh-based counterpart.
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Contributor : Habib Mehrez <>
Submitted on : Tuesday, September 20, 2016 - 3:36:35 PM
Last modification on : Friday, May 24, 2019 - 5:23:38 PM

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Vinod Pangracious, Zied Marrakchi, Habib Mehrez. Design and Optimization of a Horizontally Partitioned, High-Speed, 3D Tree-Based FPGA. IEEE Micro, Institute of Electrical and Electronics Engineers, 2015, 35 (6), pp.48--59. ⟨10.1109/MM.2014.57⟩. ⟨hal-01369167⟩

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