Efficient DVFS for low power HEVC software decoder

Abstract : Low power design is a primary concern for modern battery-driven devices and video applications such as video decoding are often the most resource intensive applications of consumer electronics devices. Modern embedded processors are now proven to support video applications with software. They are also equipped with advanced features including Dynamic Voltage Frequency Scaling and Dynamic Power Management in order to reduce their power consumption. High Efficiency Video Coding (HEVC) is the latest MPEG video standard offering state-of-the-art compression rates and advanced parallel processing solutions. This paper presents a low power real-time software architecture for a HEVC decoder. Software decoding fosters short time-to-market as it relies on software designs for a general purpose processor. The proposed architecture exploits the characteristics of the multicore ARM big.LITTLE System-on-a-Chip to provide a low power design. Extensive power measurements as well as real-time metrics are provided to compare the proposed architecture with state-of-the-art.
Type de document :
Article dans une revue
Journal of Real-Time Image Processing, Springer Verlag, 2017, 13 (1), pp.39-54. 〈10.1007/s11554-016-0624-9〉
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https://hal.archives-ouvertes.fr/hal-01354629
Contributeur : Erwan Nogues <>
Soumis le : vendredi 19 août 2016 - 10:04:43
Dernière modification le : mardi 21 novembre 2017 - 15:23:30

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Erwan Nogues, Julien Heulot, Glenn Herrou, Ladislas Robin, Maxime Pelcat, et al.. Efficient DVFS for low power HEVC software decoder. Journal of Real-Time Image Processing, Springer Verlag, 2017, 13 (1), pp.39-54. 〈10.1007/s11554-016-0624-9〉. 〈hal-01354629〉

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