Ouessant: Flexible Integration of Dedicated Coprocessors in Systems On Chip

Pierre-Henri Horrein 1, 2 Philip-Dylan Gleonec 3 Erwan Libessart 4, 2 André Lalevee 5, 2, 6 Matthieu Arzel 1, 2
1 Lab-STICC_TB_CACS_IAS
Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance
4 Lab-STICC_TB_MOM_PIM
Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance
5 ADOPNET - Advanced technologies for operated networks
IRISA-D2 - RÉSEAUX, TÉLÉCOMMUNICATION ET SERVICES, Télécom Bretagne, UR1 - Université de Rennes 1
Abstract : Integration of hardware accelerators in System on Chips is often complex. When dealing with reconfigurable hard- ware, this greatly limits the attainable flexibility. In this paper, we propose an alternative approach to the Molen paradigm [1]. This approach, named Ouessant, is based on a very simple general purpose instruction set designed for close interaction with dedicated hardware accelerators. This instruction set is used to program a dedicated controler, which commands the accelerator's execution and data transfer with minimal CPU intervention. The resulting architecture is flexible, extensible, and can be easily integrated in System on Chips. Adding new accelerators is also made easier. Implementation of the architecture on different FPGA resources show very low footprint and a very small impact on attainable performance. Ouessant is freely available under an open-source license.
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Pierre-Henri Horrein, Philip-Dylan Gleonec, Erwan Libessart, André Lalevee, Matthieu Arzel. Ouessant: Flexible Integration of Dedicated Coprocessors in Systems On Chip. DATE 2016 : Design, Automation & Test in Europe Conference & Exhibition , Mar 2016, Dresden, Germany. pp.1493 - 1496, 2016. ⟨hal-01343408⟩

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