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Conference papers

Performances comparison between Multilevel hierarchical and Mesh FPGA

Zied Marrakchi 1 Hayder Mrabet 1 Habib Mehrez 1
1 CIAN - Circuits Intégrés Numériques et Analogiques
LIP6 - Laboratoire d'Informatique de Paris 6
Abstract : In this paper we evaluate a new multilevel hierarchical FPGA (MFPGA). The specific architecture includes two unidirectional programmable networks: A downward network based on the butterfly-fat-tree topology, and a special upward network. New tools are developed to place and route several benchmark circuits on this architecture. Comparison with the traditional symmetric, Manhattan mesh architecture shows that MFPGA can implement circuits with smaller area and better speed.
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Zied Marrakchi, Hayder Mrabet, Habib Mehrez. Performances comparison between Multilevel hierarchical and Mesh FPGA. DTIS IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology, Sep 2006, Tunis, Tunisia. pp.166-171, ⟨10.1109/DTIS.2006.1708712⟩. ⟨hal-01338430⟩



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