Hierarchical Graph-Based Sizing for Analog Cells Through Reference Transistors

Abstract : In this paper, an algorithm for automatic sizing and operating point computation of hierarchical knowledge-based analog cells is presented. The algorithm assumes that an analog cell is described as a hierarchy of devices and modules inside our dedicated framework CAIRO+. Within devices, the concept of the reference transistor is elaborated. The latter is used to construct device dependency graphs for each device. Module dependency graphs are constructed by merging graphs of all children modules and devices. Inside each device, the reference transistor controls the sizing and biasing of the whole device. It propagates electrical parameters to secondary transistors. The used propagation technique ensures that all the device constraints are satisfied by construction. The algorithm was used to size and bias a two-stage single-ended OTA amplifier. It proved to be successful in DC operating point calculation in the context of hierarchical knowledge-based framework.
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Submitted on : Tuesday, June 28, 2016 - 10:56:34 AM
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Ramy Iskander, Marie-Minerve Rosset-Louërat, Andreas Kaiser. Hierarchical Graph-Based Sizing for Analog Cells Through Reference Transistors. PRIME IEEE Conference on Ph.D. Research in MicroElectronics and Electronics Winner of the Bronze Leaf Certificate, Jun 2006, Otranto, Italy. IEEE, PRIME IEEE Conference on Ph.D. Research in MicroElectronics and Electronics Winner of the Bronze Leaf Certificate, pp.321-324, 〈10.1109/RME.2006.1689961〉. 〈hal-01338246〉

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