An Efficient TLM/T Modeling and Simulation Environment Based on Conservative Parallel Discrete Event Principles

Abstract : The paper presents an innovative simulation scheme to speed-up simulations of multi-clusters multi-processors SoCs at the TLM/T (transaction level model with time) abstraction level. The hardware components of the SoC architecture are written in standard SystemC. The goal is to describe the dynamic behavior of a given software application running on a given hardware architecture (including the dynamic contention in the interconnect and the cache effects), in order to provide the system designer with the same reliable timing information as a cycle accurate simulation, with a simulation speed similar to a TLM simulation. The key idea is to apply parallel discrete event simulation (PDES) techniques to a collection of communicating SystemC SC-THREAD. Experimental results show a simulation speedup of a factor up to 50 versus a BCA simulation (bus cycle accurate), for a timing error lower than $10^{-3}$.
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Conference papers
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https://hal.archives-ouvertes.fr/hal-01338224
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Submitted on : Tuesday, June 28, 2016 - 10:33:04 AM
Last modification on : Thursday, March 21, 2019 - 2:16:19 PM

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Emmanuel Viaud, François Pêcheux, Alain Greiner. An Efficient TLM/T Modeling and Simulation Environment Based on Conservative Parallel Discrete Event Principles. DATE Design Automation and Test in Europe Conference, Mar 2006, Munich, Germany. pp.94-99, ⟨10.1109/DATE.2006.244003⟩. ⟨hal-01338224⟩

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