Configuration tools for a new multilevel hierarchical FPGA

Zied Marrakchi 1 Hayder Mrabet 1 Habib Mehrez 1
1 CIAN - Circuits Intégrés Numériques et Analogiques
LIP6 - Laboratoire d'Informatique de Paris 6
Abstract : In this paper we evaluate a new multi-level hierarchical MFPGA. The specific architecture includes two unidirectional programmable networks: A downward network based on the Butterfly-Fat-Tree topology and a special hierarchical upward network. The Downward network uses linear populated and unidirectional Switch Boxes (SBs) and gives one path from each wire-source in the top to reach a leaf (Logic Block: LB) in the lowest level. The upward network connects the LBs output and the input Pads to the SBs situated in different levels of the downward network. New tools are developed to program the new architecture. The global placement approach uses a combination of clustering and partitioning with adaptations to deal with the multi-level interconnect topology. First we run a multi-level bottom-up clustering to reduce external connections. Second we run a multi-level top-down refinement to reduce signals bandwidth of clusters in each level. A detailed placer defines the position of each LB inside a cluster and considers more complex routing constraints. The router is an adaptation of Pathfinder. The global routing consists on selecting the level to use. Signals routing is immediate since path to reach a destination is predictable and unique. Results are based on the MCNC benchmarks and they quantify the LB occupancy and routability. Comparison with the traditional symmetric Manhattan mesh architecture shows that MFPGA can implement circuits with fewer switches and a smaller total area.
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Submitted on : Tuesday, June 28, 2016 - 10:27:23 AM
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Zied Marrakchi, Hayder Mrabet, Habib Mehrez. Configuration tools for a new multilevel hierarchical FPGA. FPGA ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Feb 2006, Monterey, California, United States. ACM, FPGA ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pp.229-229, 〈10.1145/1117201.1117248〉. 〈hal-01338217〉



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