Knowledge-Aware Synthesis Using Hierarchical Graph-Based Sizing and Biasing

Abstract : The hierarchical graph-based sizing and biasing method of analog circuits has been previously developed. Its potential application in the field of knowledge-based analog synthesis is studied. This method reduces the number of optimization variables by taking into account their circuit dependency relations. This is done by automatically generating a design plan to express circuit dependencies. The design plan is then introduced into an optimization loop. The optimization engine uses the Nelder-Mead simplex method. The whole method is successfully applied to a single-ended two-stage amplifier. It produces simulator-like quality designs in a reasonable time, thus allowing interactive design of analog circuits.
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Conference papers
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https://hal.archives-ouvertes.fr/hal-01334852
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Submitted on : Tuesday, June 21, 2016 - 2:20:04 PM
Last modification on : Thursday, March 21, 2019 - 2:39:33 PM

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Ramy Iskander, Marie-Minerve Louërat, Andreas Kaiser, Dimitri Galayko. Knowledge-Aware Synthesis Using Hierarchical Graph-Based Sizing and Biasing. 50th Midwest Symposium on Circuits and Systems (MWSCAS), Aug 2007, Montréal, Québec, Canada. pp.984-987, ⟨10.1109/NEWCAS.2007.4487996⟩. ⟨hal-01334852⟩

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