Systematic Offset Detection and Evaluation Using Hierarchical Graph-Based Sizing and Biasing

Abstract : A hierarchical graph-based sizing and biasing method of analog circuits has been previously developed. However, conflicts appear in dependency graphs generated by our method due to the large number of degrees of freedom in analog design. Therefore, an enhanced method is presented that automatically detects conflicts and resolves them by inserting systematic offset voltages as additional degrees of freedom into the graph. During graph evaluation, a systematic offset is evaluated as the voltage difference between conflicting nodes, which can be eliminated by transposing it to the inputs of the circuit. As an example, we have successfully applied our method to the sizing of a single-ended two-stage operational amplifier.
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Conference papers
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https://hal.archives-ouvertes.fr/hal-01334848
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Submitted on : Tuesday, June 21, 2016 - 2:19:32 PM
Last modification on : Thursday, March 21, 2019 - 2:39:25 PM

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Ramy Iskander, Andreas Kaiser, Marie-Minerve Louërat. Systematic Offset Detection and Evaluation Using Hierarchical Graph-Based Sizing and Biasing. 14th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Dec 2007, Marrackech, Morocco. pp.170-173, ⟨10.1109/ICECS.2007.4510957⟩. ⟨hal-01334848⟩

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