Hybrid-Timing FIFOs to use on Networks-on-Chip in GALS Architectures

Abstract : This paper presents three high-throughput low-latency FIFOs that can be used as efficient and reliable interfaces between different domains in hybrid-timing systems. These three hardware components have been designed to be used in a Globally Asynchronous Locally Synchronous clusterized Multi-Processor System-on-Chip communicating by a Multi-Synchronous or by a fully Asynchronous Network-on-Chip. The proposed architectures are rather generic and allow the system designer to make various trade-off between latency and robustness, depending on selected synchronizer. These FIFOs have been physically implemented with portable ALLIANCE CMOS standard cell library and the architectures have been evaluated by SPICE simulation for a 90nm CMOS fabrication process.
Document type :
Conference papers
Complete list of metadatas

https://hal.archives-ouvertes.fr/hal-01311526
Contributor : Lip6 Publications <>
Submitted on : Wednesday, May 4, 2016 - 1:18:13 PM
Last modification on : Thursday, March 21, 2019 - 1:04:47 PM

Identifiers

  • HAL Id : hal-01311526, version 1

Citation

Abbas Sheibanyrad, Alain Greiner. Hybrid-Timing FIFOs to use on Networks-on-Chip in GALS Architectures. ESA International Conference on Embedded Systems and Applications, Jun 2007, Las Vegas, Nevada, United States. pp.27-33. ⟨hal-01311526⟩

Share

Metrics

Record views

54