Generic Techniques and CAD tools for automated generation of FPGA Layout

Husain Parvez 1 Hayder Mrabet 1 Habib Mehrez 1
1 CIAN - Circuits Intégrés Numériques et Analogiques
LIP6 - Laboratoire d'Informatique de Paris 6
Abstract : This paper presents an automated method of generating an FPGA layout. The main purpose of developing a generator is to reduce the overall FPGA design time with limited area penalty. This generator works in two phases. In the first phase, it generates a partial layout using generic parameterized algorithms. The partial layout is generated to obtain a fast bitstream configuration mechanism, an efficient power routing and a balanced clock distribution network. In the second phase, the generator completes the remaining layout using automatic placer and router. This two-phase technique allows better maneuvering of the layout according to initial constraints. The proposed method is validated by generating the layout of an island-style FPGA which includes hardware support for the mitigation of Single Event Upsets (SEU). The FPGA layout is generated using a symbolic standard cell library which allows easy migration to any layout technology. This layout is successfully migrated to 130 nm technology.
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Conference papers
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https://hal.archives-ouvertes.fr/hal-01301526
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Submitted on : Tuesday, April 12, 2016 - 2:04:56 PM
Last modification on : Thursday, March 21, 2019 - 1:09:06 PM

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Husain Parvez, Hayder Mrabet, Habib Mehrez. Generic Techniques and CAD tools for automated generation of FPGA Layout. PRIME IEEE Conference on Ph.D. Research in MicroElectronics and Electronics, Jun 2008, Istanbul, Turkey. pp.141-144, ⟨10.1109/RME.2008.4595745⟩. ⟨hal-01301526⟩

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