Efficient Tree Topology for FPGA Interconnect Network

Abstract : This paper presents an improved Tree-based architecture that unifies two unidirectional programmable networks: A predictible downward network based on the Butter y-Fat-Tree topology, and an upward network using hierarchy. Studies based on Rent's Rule show that switch requirements in this architecture grow slower than in traditional Mesh topologies. New tools are developed to place and route several benchmark circuits on this architecture. Experimental results show that the Tree-based architecture can implement MCNC benchmark circuits with an average gain of 54% in total area compared with Mesh architecture.
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Conference papers
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https://hal.archives-ouvertes.fr/hal-01301523
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Submitted on : Tuesday, April 12, 2016 - 1:59:58 PM
Last modification on : Thursday, March 21, 2019 - 1:09:05 PM

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Zied Marrakchi, Hayder Mrabet, Emna Amouri, Habib Mehrez. Efficient Tree Topology for FPGA Interconnect Network. GLSVLSI ACM Great Lakes Symposium on VLSI, May 2008, Orlando, Florida, United States. pp.321-326, ⟨10.1145/1366110.1366186⟩. ⟨hal-01301523⟩

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