Use of Redundant Arithmetic on Architecture and Design of a High Performance DCT Macro-bloc Generator

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Conference papers
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https://hal.sorbonne-universite.fr/hal-01265641
Contributor : Roselyne Chotin <>
Submitted on : Monday, February 1, 2016 - 1:41:56 PM
Last modification on : Thursday, March 21, 2019 - 2:30:34 PM

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  • HAL Id : hal-01265641, version 1

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Roselyne Chotin, Yannick Dumonteix, Habib Mehrez. Use of Redundant Arithmetic on Architecture and Design of a High Performance DCT Macro-bloc Generator. 15th Design of Circuits and Integrated Systems Conference (DCIS), 2000, Montpellier, France. pp.428-433. ⟨hal-01265641⟩

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