Skip to Main content Skip to Navigation
Conference papers

Worst-Case Communication Overhead in a Many-Core based Shared-Memory Model

Abstract : With emerging many-core architectures, using on-chip shared memories is an interesting approach because it provides high bandwidth and high throughput data exchange. Such a feature is usually implemented as a multi-bus multi-banked memory. Since predicting timing behavior is key to efficient design and verification of embedded real-time systems, the question that arises is how to evaluate the access time for one memory access of a given task while others may concurrently access the same memory-bank at t the same time. In this paper, we give the answers for a subset of streaming applications modeled like CSDF Model of Computation and implemented in Kalray’s MPPA chip.
Complete list of metadata

Cited literature [11 references]  Display  Hide  Download
Contributor : Open Archive Toulouse Archive Ouverte (oatao) <>
Submitted on : Wednesday, December 9, 2015 - 10:07:13 AM
Last modification on : Friday, June 25, 2021 - 9:48:03 AM
Long-term archiving on: : Saturday, April 29, 2017 - 9:47:00 AM


Files produced by the author(s)


  • HAL Id : hal-01239714, version 1
  • OATAO : 12711


Amira Dkhil, Stéphane Louise, Christine Rochange. Worst-Case Communication Overhead in a Many-Core based Shared-Memory Model. 7th Junior Researcher Workshop on Real-Time Computing (JRWRTC 2013), Oct 2013, Sophia Antipolis, France. pp.53-56. ⟨hal-01239714⟩



Record views


Files downloads