Use Them -Don't Waste Them. Recruiting Strong ECC in L1 Caches for Hard Error Recovery Without the Penalty
Résumé
Operating below nominal voltage levels is a promising direction to enable ultra-low power CMOS-based sytems. This is true due to the cubic relation between the dynamic power consumption and the supply voltage. The main roadblock during aggressive voltage scaling is that the reliability of the circuits and especially of memory structures (SRAM cells) is exponentially decreased. The usage of well-known error correction codes (ECC) can only remedy a part of the problem. ECC have been proposed to protect the lower level caches (e.g., L2 or L3), but ECC cannot be employed in single-cycle first level caches due to their performance sensitivity to the additional latency of ECC. In this work, we propose a methodology to solve this problem by exploring the use of criticality metrics in aggressive superscalar processors. Instead of disabling the faulty frames of a faulty cache (as proposed in related work), we keep these frame " alive " (data are still placed and accessed in these faulty frames) and we use strong ECC to correct the hard multibit errors. The key idea is to direct to faulty cache frames data that can be delayed for one or more cycles without affecting program completion time i.e., instructions considered to not be on the critical path of the program execution. The basic mechanisms for hardening first level faulty caches with strong ECC protection without inflating program executing time are described in this position paper.
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