LDPC decoder architecture for DVB-S2 and DVB-S2X standards

Cédric Marchand (1) , Emmanuel Boutillon (1)

1 Lab-STICC_UBS_CACS_IAS

A particular type of conflict due to multiple-diagonal sub-matrices in the DVB-S2 parity-check matrices is known to complicate the implementation of the layered decoder architecture. The new matrices proposed in DVB-S2X no longer use such sub-matrices. For implementing a decoder compliant both with DVB-S2 and DVB-S2X, we propose an elegant solution which overcomes this conflicts relying on an efficient write disable of the memories, allowing a straightforward implementation of layered LDPC decoders. The complexity and latency are further reduced by eliminating one barrel shifter. Compared with the existing solutions, complexity is reduced without performance degradation. Keywords—Low-Density Parity-Check (LDPC) code, memory conflict, layered decoder, DVB-S2, DVB-S2X.

Domaines: Electronique

Cédric Marchand, Emmanuel Boutillon. LDPC decoder architecture for DVB-S2 and DVB-S2X standards. 2015 IEEE International Workshop on Signal Processing Systems, SIPS 2015, IEEE, Oct 2015, Hangzhou, China. ⟨hal-01216516⟩