Voltage Overscaling Algorithms for Energy-Efficient Workflow Computations With Timing Errors

Aurélien Cavelan (1, 2) , Yves Robert (1, 2) , Hongyang Sun (1, 2) , Frédéric Vivien (1, 2)

1 LIP - Laboratoire de l'Informatique du Parallélisme
2 ROMA - Optimisation des ressources : modèles, algorithmes et ordonnancement

We propose a software-based approach using dynamic voltage overscaling to reduce the energy consumption of HPC applications. This technique aggressively lowers the supply voltage below nominal voltage, which introduces timing errors , and we use Algorithm-Based Fault-Tolerance (ABFT) to provide fault tolerance for matrix operations. We introduce a formal model, and we design optimal polynomial-time solutions, to execute a linear chain of tasks. Evaluation results obtained for matrix multiplication demonstrate that our approach indeed leads to significant energy savings, compared to the standard algorithm that always operates at nominal voltage.

Keywords: Timing errors; ABFT; voltage overscaling; energy efficiency

Domains: Data Structures and Algorithms [cs.DS]; Modeling and Simulation; Performance [cs.PF]

Aurélien Cavelan, Yves Robert, Hongyang Sun, Frédéric Vivien. Voltage Overscaling Algorithms for Energy-Efficient Workflow Computations With Timing Errors. FTXS '15: 5th Workshop on Fault Tolerance for HPC at eXtreme Scale, Jun 2015, Portland, United States. pp.8, ⟨10.1145/2751504.2751508⟩. ⟨hal-01199250⟩