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Article Dans Une Revue Parallel Processing Letters Année : 2001

The Barrier-Lock Clock: A Scalable Synchronisation-oriented Logical Clock

Denis Poitrenaud
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Pierre Sens
Bertil Folliot
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Résumé

In this article, we introduce a new logical clock, the barrier-lock clock, whose conception is based on the lazy release consistency memory model (LRC) supported by several distributed shared memory (DSM) systems. Since in the LRC, the propagation of shared memory updates performed by the processes of a parallel application is induced by lock and barrier operations, our logical clock has been modeled on those operations. Each barrier-lock times-tamp encodes the synchronization operation with which it is associated. Its size is not dependent on the number of processes of the system, as the traditional logical vector clocks, but it is proportional to the number of locks. The barrier-lock time characterizes the causality of shared memory updates performed by processes of a parallel application running on a LRC-based DSM system. A formal proof and experimental tests have confirmed such property.
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Dates et versions

hal-01198738 , version 1 (14-09-2015)

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Citer

Luciana Arantes, Denis Poitrenaud, Pierre Sens, Bertil Folliot. The Barrier-Lock Clock: A Scalable Synchronisation-oriented Logical Clock. Parallel Processing Letters, 2001, 11 (1), pp.65-76. ⟨10.1142/S0129626401000439⟩. ⟨hal-01198738⟩
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