Fast multidimensional optimization of analog circuits initiated by monodimensional global Peano explorations

Akram Malak , Yao Li (1) , Ramy Iskander (1) , François Durbin , Farakh Javid , Marie-Minerve Louërat (1) , André Tissot , Jean-Marc Guebhard

1 CIAN - Circuits Intégrés Numériques et Analogiques

A fast design space exploration of analog firm intellectual properties (IP) based on Peano-like paths (piecewise linear and monodimensional) is presented. First, the n-dimensional design space is globally explored following those Peano curves, which are obtained by varying only 1 design variable at a time using a fixed step size. Each variable is taken within a given range. During exploration, the best x-percentile points are retained. After varying globally the n variables, a Nelder–Mead simplex optimization is performed using each of the best points as an initial point. Successive p-variable partitioning of the n -dimensional design space (with p⪯¡n) are applied to adapt the simplex optimization to large dimensions. The proposed exploration technique is combined with a simulation-based hierarchical sizing and biasing methodology to size and bias analog firm IPs. This combined approach has been successfully applied to size and bias a Constant Voltage Reference (CVR) in a 5 V SOI 1um technology. The results illustrate the effectiveness and accuracy of the proposed approach.

Domaines: Informatique [cs]

Akram Malak, Yao Li, Ramy Iskander, François Durbin, Farakh Javid, et al.. Fast multidimensional optimization of analog circuits initiated by monodimensional global Peano explorations. Integration, the VLSI Journal, 2015, 48, pp.198-212. ⟨10.1016/j.vlsi.2014.04.002⟩. ⟨hal-01195956⟩