A defect-tolerant area-efficient multiplexer for basic blocks in SRAM-based FPGAs
Résumé
As CMOS feature sizes decrease into nanometers, manufacturing defects are becoming a growing concern in electronics industry. SRAM-based FPGAs, which have been widely used in many applications, are also affected by technology downscaling. Since the cornerstone of their logic and interconnect resources is the multiplexer, this work introduces a defect-tolerant multiplexer, more resilient to single transistor defects (stuck-open, stuck-closed and gate shorts) than other multiplexer architectures studied in the paper, and more area-efficient than other existent hardening techniques.