Skip to Main content Skip to Navigation
New interface
Journal articles

Real-time H.264/AVC baseline decoder implementation on TMS320C6416

Abstract : The H.264/AVC Advanced Video Coding standard (AVC) is poised to enable a wide range of applications. However, its increased complexity creates a big challenge for efficient software implementations. This work develops and optimises the H.264/AVC video decoder level two on the TMS320C6416 Digital Signal Processor (DSP) for video conference applications. In order to accelerate the decoding speed, several algorithmic optimisations have been ported to inverse entropy decoding and intra-prediction modules. The parallelism between algorithm execution and data transfers was fully exploited using Enhanced Direct Memory Access (EDMA) engine. Furthermore, based on the DSP architectural features, various core-specific optimisation techniques were adopted leading to an increase in speed by up to 70%. Intensive experimental tests prove that a real-time decoding on TMS320C6416 DSP running at 720 MHz is obtained for Common Intermediate Format resolution (CIF 352 × 288)
Document type :
Journal articles
Complete list of metadata
Contributor : Thierry Grandpierre Connect in order to contact the contributor
Submitted on : Thursday, September 3, 2015 - 3:36:43 PM
Last modification on : Thursday, September 29, 2022 - 2:21:15 PM

Links full text



Imen Werda, Taheni Dammak, Thierry Grandpierre, Mohamed Ali Ben Ayed, Nouri Masmoudi. Real-time H.264/AVC baseline decoder implementation on TMS320C6416. Journal of Real-Time Image Processing, 2012, 7 (4), pp.215-232. ⟨10.1007/s11554-010-0181-6⟩. ⟨hal-01192810⟩



Record views